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ISL8201M
If the output is pre-biased to a voltage above the expected
value (as shown Figure 18), neither MOSFET will turn on until
the end of the soft-start, at which time it will pull the output
voltage down to the final value. Any resistive load connected
to the output will help pull down the voltage (at the RC rate of
the R of the load and the C of the output capacitance).
ISET
FIGURE 15. I SET AND SOFT-START OPERATION
Soft-Start and Pre-Biased Outputs
The soft-start internally ramps the reference on the
non-inverting terminal of the error amp from 0V to 0.6V in a
nominal 6.8ms. The output voltage will thus follow the ramp,
from zero to final value, in the same 6.8ms (the actual ramp
seen on the V OUT will be less than the nominal time), due to
some initialization timing, between T 3 and T 4 .
The ramp is created digitally, so there will be 64 small
discrete steps. There is no simple way to change this ramp
rate externally.
After an initialization period (T 3 to T 4 ), the error amplifier
(COMP/EN pin) is enabled and begins to regulate the
converter's output voltage during soft-start. The oscillator's
triangular waveform is compared to the ramping error amplifier
voltage. This generates PHASE pulses of increasing width that
charge the output capacitors. When the internally generated
soft-start voltage exceeds the reference voltage (0.6V), the soft-
start is complete and the output should be in regulation at the
expected voltage. This method provides a rapid and controlled
output voltage rise; there is no large inrush current charging the
output capacitors. The entire start-up sequence from POR
typically takes up to 17ms; up to 10.2ms for the delay and OCP
sample and 6.8ms for the soft-start ramp.
Figure 16 shows the normal curve for start-up; initialization
begins at T 0 , and the output ramps between T 1 and T 2 . If the
output is pre-biased to a voltage less than the expected
value (as shown Figure 17), the ISL8201M will detect that
condition. Neither internal MOSFET will turn on until the
soft-start ramp voltage exceeds the output; V OUT starts
seamlessly ramping from there.
9
FIGURE 16. NORMAL START-UP
FIGURE 17. PRE-BIASED START-UP
FN6657.2
October 21, 2010
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